http://www.wucan.net/ zh-cn PBlog2 v2.4 http://www.wucan.net/images/logos.gif http://www.wucan.net/ Android培训,Fpga培训,Mtk培训 http://www.wucan.net/default.asp?id=3 officeoffice@126.com(admin) Sat,10 Oct 2009 16:14:47 +0800 http://www.wucan.net/default.asp?id=3 Cadence培训高级班
课程目标
Cadence培训高级班将首先让您了解CB板上出现的信号反射、串扰、电源/地平面干扰、时序匹配以及电磁兼容性等一系列问题产生的机理，并掌握其解决方法；然后讲解并上机练习Cadence的高速 PCB设计与仿真工具SPECCTRAQuest的使用。使您在硬件设计过程中，能够达到“设计即正确”的目的。

    培养对象
        在工作实践中遇到了高速数字电路与高速PCB设计问题；对高速PCB设计感兴趣的硬件工程师；已经具备一定的硬件开发经验，需要增加就业竞争力的在校硕士及博士研究生；具备非常扎实的电子工程基本知识，并积累了相当程度的硬件工程师工作经验的在校本科生。

    班级规模及环境
        为了保证培训效果，增加互动环节，我们坚持小班授课，每期报名人数限5人，多余人员安排到下一期进行。

    质量保障
        1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
        2、培训结束后免费提供一个月的技术支持，充分保证培训后出效果；
        3、培训合格学员可享受免费推荐就业机会。

    教学时间，教学地点
            上课地点：华东师范大学／银城大厦（上海市，地铁3号线或4号线金沙江路站旁）
            最近开班有周末班/连续班/晚班
    学时
　　课时： 共9天，每天8学时，总计72学时

        ◆外地学员：代理安排食宿（需提前预定）
        ☆合格学员免费颁发相关资格证书，提升您的职业资质
        作为最早专注于嵌入式培训的专业机构，曙海嵌入式学院提供的证书得到本行业的广泛认
        可，学员的能力得到大家的认同。
        ☆合格学员免费推荐工作  
    课程进度安排
课程大纲
第一阶段

1 高速PCB设计中的理论基础
    传输线理论、信号完整性（反射、串扰、过冲、地弹、振铃等）、电磁兼容性和时序匹配等等。
2 SPECCTRAQuest设计流程
    2.1 Pre-Placement
    2.2 Board Setup Requirements for Extracting and Applying Topologies
    2.3 Database Setup Advisor
        —Cross-Section
        —DC Nets
        —DC Voltages
        —Device Setup . ??—SI Models
        —SI Audit


3 拓扑结构的抽取与仿真 Extracting and Simulating Topologies
    3.1 Pre-Route Extraction Setup—Default Model Selection.
    3.2 Pre-Route Extraction Setup—Unrouted Interconnect
    3.3 Pre-Route Template Extraction
    3.4 SQ Signal Explorer Expert
    3.5 Analysis Preferences
    3.6 SigWave
    3.7 Delay Measurements


第二阶段

4 确定和施加约束 Determining and Adding ConstraintsSolution
    4.1 Solution SpaceAnalysis: Step 1 to 6
    4.2 Parametric Sweeps.
    4.3 Constraints :
        Topology Template Constraints
        Switch/Settle Constraints
        Assigning the Prop Delay Constraints
        Impedance Constraint
        Relative Propagation Delay Constraint
        Diff Pair Constraints
        Max Parallel Constraint
        Wiring Constraint
        User-Defined Constraint
        Signal Integrity Constraints
    4.4 Usage of Constraints Defined in Topology Template


5 模板应用和基于约束的布局
    Template Applications and Constraint-Driven Placement
    5.1 Creating a Topology
    5.2 Wiring the Topology
    5.3 TLines and Trace Models
    5.4 Coupled Traces
    5.5 RLGC Matrix of Coupled Trace Models
    5.6 Crosstalk Simulation in SQ Signal Explorer Expert
    5.7 Simulating with Coupled-Trace Models
    5.8 Sweep Simulation Results with Coupled-Trace Models
    5.9 Extracting a Topology Using the Constraint Manager
    5.10 Electrical Constraint Set
    5.11 Applying Electrical CSet
    5.12 Worksheet Analysis
    5.13 Spacing and Physical Rule Sets
    5.14 Electrical Rule Set


第三阶段

6 基于约束的布线 Constraint-Driven Routing
    6.1 Manual Routing
    6.2 Routing with the SPECCTRA Smart Route
    6.3 Driving Constraints in Routing
7 布线后的DRC检查和分析 Post-Route DRC and Analysis
    7.1 Post-Route Analysis
    7.2 SigNoise
    7.3 Reflection Simulation
    7.4 Reflection Waveform Analysis
    7.5 Comprehensive Simulation
    7.6 Crosstalk Simulation
    7.7 Crosstalk Analysis
    7.8 Simultaneous Switching Noise Simulation
    7.9 SSN Waveform Analysis
    7.10 System-Level Analysis
    7.11 A Complete Design Link
    7.12 Initialize Design Link


8 差分信号设计 Differential Pair Design Exploration
    8.1 Types of Differential Pairs in SPECCTRAQuest
    8.2 Create Differential Pair Using SPECCTRAQuest
    8.3 Create Differential Pair Using Constraint Manager
    8.4 Assigning Differential Pair Signal Models
    8.5 Preference to Extract Unrouted Differential Pair Topology
    8.6 Extracting Unrouted Differential Pair Topology
    8.7 Custom Stimulus to Analyze Differential Pair Topology
    8.8 Differential Pair Topology Analysis
    8.9 Coupled Trace Model and Differential Pair Topology
    8.10 Layout Cross-section Editor
    8.11 Differential Pair Constraints
    8.12 Differential Pair Constraints in the Constraint Manager
    8.13 Differential Pair Analysis in the Constraint Manager
    8.14 Post Route Extraction
热线：021-51875830 62450161
传真：021-62450161
业务手机:15921673576
详情请访问网站：http://www.51qianru.cn

]]> http://www.wucan.net/default.asp?id=2 officeoffice@126.com(admin) Sat,10 Oct 2009 16:13:03 +0800 http://www.wucan.net/default.asp?id=2 深圳MTK培训
广州MTK培训
深圳FPGA培训
Cadence培训初级班
课程目标
        Cadence培训初级班主要为您介绍从原理图输入到印刷电路板光绘制造文件输出的全线PCB设计流程，通过讲课及上机练习相结合的方式完成Cadence的原理图工具Concept- HDL、PCB工具Allegro以及相应的建库工具的使用方法的系统培训。通过培训学员可掌握先进的Cadence PCB设计流程，完成PCB设计。

    培养对象
        从事硬件开发的所有人员，以及具有一定基础的高年级本科生或者硕、博士研究生。

    班级规模及环境
        为了保证培训效果，增加互动环节，我们坚持小班授课，每期报名人数限5人，多余人员安排到下一期进行。

    质量保障
        1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
        2、培训结束后免费提供一个月的技术支持，充分保证培训后出效果；
        3、培训合格学员可享受免费推荐就业机会。

    时间地点
上课地点：华东师范大学／银城大厦（上海市，地铁3号线或4号线金沙江路站旁）
  最近开班有周末班/连续班/晚班
    学时和费用
        ★课时： 共9天，总计72学时;

        ◆外地学员：代理安排食宿（需提前预定）
        ☆合格学员免费颁发相关资格证书，提升您的职业资质
        作为最早专注于嵌入式培训的专业机构，曙海嵌入式学院提供的证书得到本行业的广泛认
        可，学员的能力得到大家的认同。
        ☆合格学员免费推荐工作  
    课程进度安排
课程大纲
第一阶段

1 Concept HDL基本设计流程
    Concept HDL Basic Board Design Flow
2 设计输入 Design Entry
    2.1 Project Setup
    2.2 Editing a Schematic - Part Libraries, Adding Parts, Adding Wires,Naming Wires
    2.3 Concept Error Checking
    2.4 Design Libraries
    2.5 Working with Groups
    2.6 Copying, Adding, Inserting, and Moving PagesDeleting Pages
    2.7 The CheckPlus Tool
    2.8 Cross Referencing Signals
    2.9 Plotting the Schematic
    2.10 Part Tables
    2.11 Packaging
    2.12 Bill of Materials


3 从原理图到PCB：PackageXL 工具使用
    3.1 Introduction to Board Layout
    3.2 Mainstream Board Design
    3.3 Design Synchronization
    3.4 Netlist Files
    3.5 Export Physical
4 层次化设计 Hierarchical Design
    4.1 Components of a Hierarchical Block
    4.2 Creating Hierarchical Block Symbols
    4.3 Top-Down Design


第二阶段

5 PCB设计准备：Allegro环境、规则设置、PCB布局布线
    5.1 Allegro User Interface
    5.2 Managing the Allegro Work Environment
    5.3 Padstack Designer
    5.4 Component Symbols
    5.5 Board Design Files
    5.6 Importing Logic Information into Allegro
    5.7 Setting Design Constraints
    5.8 Component Placement
    5.9 Routing and Glossing


6 建立元件库 PCB Librarian Expert
    6.1 Design Processes and Library Models
    6.2 Setting Up a Build Area
    6.3 The Symbol View
    6.4 The Chips View
    6.5 The Part Table View
    6.6 The Simulation View
    6.7 Testing the Part
    6.8 Creating a Split Part
    6.9 Importing Text Files


第三阶段

7 PCB数据后处理：覆铜、生产加工数据输出
    7.1 Copper Areas and Positive or Negative Planes
    7.2 Preparing for Post Processing
    7.3 Renaming Reference Designators
    7.4 Backannotation


    7.5 Creating Silkscreens
    7.6 Creating Checkplots
    7.7 Generating Artwork
    7.8 The Aperture File
    7.9 Film Control
    7.10 Generating Gerber Files
    7.11 Creating Fabrication Drawings
    7.12 Generating an NC Drill File
    7.13 Creating the Parameters File
    7.14 Creating Assembly Drawings

热线：021-51875830 62450161
传真：021-62450161
业务手机:15921673576
详情请访问网站：http://www.51qianru.cn
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